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[Other resource] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。
Platform: | Size: 1740 | Author: 左麟 | Hits:

[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[VHDL-FPGA-Verilog] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152576 | Author: 冯申 | Hits:

[VHDL-FPGA-Verilog] Fir

Description: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 1024 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.
Platform: | Size: 5120 | Author: fredyu | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] halfband

Description: verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
Platform: | Size: 1024 | Author: lv | Hits:

[VHDL-FPGA-Verilog] adder

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 1024 | Author: surya | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Platform: | Size: 12288 | Author: 田文军 | Hits:

[Communication-Mobile] fir

Description: 用verilog实现fir滤波器,实现了一个8阶的fir滤波器-design the fir filter use verilog lanuage
Platform: | Size: 1024 | Author: 叶敏 | Hits:

[VHDL-FPGA-Verilog] DA_FIR_VERILOG

Description: 基于DA算法的FIR滤波器的verilog实现-DA-based FIR filter algorithm to achieve the verilog
Platform: | Size: 1024 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] verilog-fir

Description: 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
Platform: | Size: 2048 | Author: | Hits:

[File Format] filter

Description: verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
Platform: | Size: 1024 | Author: 艾斯 | Hits:

[Software Engineering] CODE-for-FIR-filter

Description: code for FIR filter using verilog hardware descrption language
Platform: | Size: 1024 | Author: ARULKUMAR | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: 基于Verilogfir 滤波器，含低通、带通-a fir filter base on FPGA verilog software
Platform: | Size: 2048 | Author: LIU WEI | Hits:

[Other] 基于FPGA和IP核的FIR低通滤波器

Description: 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
Platform: | Size: 39936 | Author: 曾今的1994 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR filter in verilog for xilinx ise design suit
Platform: | Size: 190464 | Author: addy007 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir滤波器的简单实现，主要用于学习与理解(Simple implementation of the fir filter, mainly for learning and understanding)
Platform: | Size: 1024 | Author: 未曾走远 | Hits:

[VHDL-FPGA-Verilog] FIR设计实现sgh

Description: FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Platform: | Size: 25600 | Author: 韩冻少 | Hits:

[hardware design] fir滤波器

Description: FIR滤波器，verilog编写，可以正常使用(FIR filter, written by verilog, can be used normally, very good)
Platform: | Size: 1031168 | Author: happytian | Hits:
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